1. Technical Field
This invention relates generally to a frequency synthesizer and, more particularly, to a low noise high speed frequency synthesizer employing a learning sequence to enable high speed tuning of the frequency synthesizer to a commanded frequency.
2. Discussion Of The Related Art
Frequency synthesizers are known in the art for producing a desired output frequency which is an integral multiple of its reference frequency. The typical frequency synthesizer employs a phase-locked loop (PLL) for producing the desired output frequency. When configured as a frequency synthesizer, a PLL 10, as shown in FIG. 1, generally consists of a phase detector 12, a loop filter 14, a voltage controlled oscillator (VCO) 16 and a digital divider 18. In this configuration, the VCO 16 is operated at N times the reference frequency (f.sub.r) and divided by N in the digital divider 18.
In operation, the output signal of the phase detector 12 consists of a DC component and an AC component. The DC component is proportional to the phase difference between the reference frequency and the closed loop frequency, while the AC component consists of remaining components from the reference frequency and its harmonics. The loop filter 14 removes the AC components and also acts as an integrator, thereby leaving only a DC control voltage. It should be noted that for reasons of clarity, the low pass filtering section of the loop filter 14, which does not bear fundamentally on the operation of the PLL 10, is not shown in FIGS. 1 through 4. The DC control voltage drives the VCO 16 to a commanded output frequency of N times the reference frequency (f.sub.r). Later, if a new commanded frequency is desired, the digital divider 18 is adjusted by a command signal resulting in a change of the phase angle between the reference frequency and the closed-loop frequency. This in turn produces a change in the DC control voltage applied to the VCO 16, which subsequently drives the VCO 16 to a new commanded frequency.
To decrease the time it takes to tune the VCO 16 to the commanded frequency, thereby creating a high speed frequency synthesizer, coarse tuning is commonly employed, as shown in FIG. 2. A coarse-tune digital-to-analog converter (D/A) 20 rapidly tunes the VCO 16 to approximately the correct frequency, thus reducing the total time required to achieve the commanded frequency within the required accuracy. To further reduce this time, the accuracy of the coarse tune D/A 20 can be enhanced by learning circuits.
A learning circuit 21, shown in FIG. 2, uses both a coarse tune digital-to-analog converter (D/A) 20 and a fine tune digital-to-analog converter (D/A) 22 employing a learning sequence. This learning sequence memorizes a high speed fine tune signal which is used to more accurately tune the VCO 16 to the commanded frequency. Thus, later when the frequency synthesizer is commanded to a frequency at which learning has occurred, the memorized value is pulled from memory to set the VCO 16 to substantially the commanded frequency.
During a tuning sequence, the coarse tune D/A 20 and the digital divider 18 are both adjusted by command signals to tune the VCO 16 to the commanded frequency. A high speed coarse tune signal from the coarse tune D/A 20 is initially summed to the VCO 16 to set the VCO 16 to substantially the commanded frequency without the need for closed-loop tuning. The initial high speed course tune signal from the coarse tune D/A 20 thereby increases the overall tuning speed of the frequency synthesizer.
If the VCO 16 is not tuned substantially on the commanded frequency, a correction signal will be detected at the output of the loop filter 14. This correction signal is then applied to a fine tune analog-to-digital converter (A/D) 24 and stored in a random access memory (RAM) 26 until the next time the frequency synthesizer is commanded to the learned frequency. When the frequency synthesizer is commanded to the learned frequency, the digitized correction value stored in the RAM 26 is applied to the fine tune (D/A) 22 and its corresponding high speed fine tune signal is summed with the high speed coarse tune signal from the coarse tune (D/A) 20. The resultant high speed tuning signal is summed to the VCO 16, which should ideally tune the VCO 16 to the commanded frequency without the need for closed-loop tuning.
The learning circuit 21 meets the objective of having a very fast open-loop tuning resulting in very fast synthesizer tuning. However, the circuit 21 has several drawbacks inherent within its design. A first drawback is that noise on the D/A outputs, i.e., thermal noise, flicker noise, etc., is often high enough to adversely affect the synthesized spectrum. While special low noise D/A's could be designed, they would tend to be high power devices and thus not readily available. Since low noise D/A's are high power devices they are also unusable in many applications due to power or cooling restrictions. Furthermore, since noise density information for D/A's is generally not defined in D/A specification sheets or available from the manufacturer, the process of finding a low noise D/A is difficult. Therefore, many times a satisfactory circuit is not available for commercial use. Another drawback is that if any imperfections exist in the fine tune A/D 24 or D/A 22, the fine tune A/D 24 will always read this imperfection and place it back into the learning sequence. Thus, a correction signal from the phase detector 12 will always be required to make up any imperfections that exist in the fine tune A/D 24 and D/A 22.
To resolve the second drawback, the learning circuit 21 can be modified, as shown in FIG. 3, by relocating the point where the fine tune A/D 24 measures the total correction signal to a point where there is only an incremental correction signal. This incremented correction signal is then read and placed into an accumulator 28 which essentially increments the RAM 26 up or down depending on the incremental correction signal. The circuit 21 therefore removes any error that might result because of any imperfections that exist in the fine tune A/D 24 and D/A 22, thereby making the circuit 21 more accurate. However, use of this circuit results in greater complexity. Furthermore, the circuit 21 still includes the noise generated by the coarse tune D/A 20 and fine tune D/A 22 during steady-state operation of the frequency synthesizer.
To remove the noise sources during steady-state operation of the PLL 10 once tuning and phase-lock has been achieved, a different circuit is required. FIG. 4 shows a circuit 29 capable of performing these operations. A detailed discussion of the circuit 29 can be found in an article by Egan, William, "LOS Shared Circuitry To Synthesize 4 Frequencies", Microwaves, May, 1979. Essentially, the circuit 29 places a high speed tuning signal from the coarse tune D/A 20 on a capacitor 30 in the loop filter 14. Afterward, the coarse tune D/A 20 is removed from the circuit by a switch 32 thereby leaving only a high speed tuning voltage from the capacitor 30 on the VCO 16. Thus, the circuit 29 resolves the drawback of having a noise source in the circuit during steady-state operation after initial high speed open-loop tuning has occurred. However, the circuit 29 does not employ a learning sequence, nor is there a location to detect the error (correction signal) from the high speed open-loop tuning. Therefore, no learning of the correction signal occurs and subsequently any correction required to tune the VCO 16 to the commanded frequency must be made up by the phase detector 12 each time tuning to the commanded frequency occurs. This in turn makes tuning to a commanded frequency much slower and less efficient.
The existing circuits described each tunes the frequency synthesizer to a commanded frequency. However, each circuit has drawbacks associated with its use that affect either the accuracy, cost, noise problems, tuning speed, or any combination thereof. What is needed then is a low noise high speed frequency synthesizer which is capable of fast tuning to substantially the commanded frequency; capable of isolating noise sources during its steady-state operation; and capable of detecting a correction signal and employing it in subsequent tuning sequences. It is therefore an object of the present invention to provide such a device.